The present invention pertains to an apparatus for the input and output of signals to and from an electronic circuit. More particularly, the present invention pertains to providing electronic circuitry for the latching of data in the input/output pad buffer cells of an integrated circuit or the like.
Electronic circuits, such as integrated circuits, typically include a die in which a number of circuit elements are placed. The die is then incorporated into a package with pins or lands for coupling to other devices and integrated circuits (e.g., via a printed circuit board). Referring to FIG. 1, a typical integrated circuit (IC) package is shown. A die 1 is coupled to the upper surface of a support structure 5. Electronic circuits on die 1 are coupled with a bond wire 2, through support structure 5, to a connector 6, such as a pin for insertion into a board or a land for electrical coupling to the board using a land grid array or ball grid array as is known in the art.
Referring to FIG. 2, a plan view of die 1 (FIG. 1) is shown. In this example, die 1 includes a core logic area 11 and a number of input/output (I/O) pad buffer cells (e.g., I/O pad buffer cell 12). An I/O pad buffer cell includes a pad for electrical coupling to a bond wire (e.g., bond wire 2 in FIG. 1) and may include circuitry for buffering the incoming and outgoing signals. For example, a data signal received from bond wire 2 passes through a pad in I/O pad buffer cell 12 and then through a buffering circuit. The resulting signal is then passed through a conductive trace (e.g., trace 14a) to receive latches 13 in core logic area 11. Also, data to be output through I/O pad buffer cell 12, is transferred from core logic area 11 through another conductive trace (e.g., trace 14b) to a separate buffering circuit on cell 12 and on to the pad and bond wire.
One characteristic that may be seen with integrated circuits of this type is that the traces coupling each pad buffer cell 12 to core logic area 11 may not be precisely matched (e.g., have the same length). Thus, if several bits of data are received in parallel in several of the I/O pad buffers, each bit will arrive at different times at receive latches 13. This is commonly referred to as skew. Furthermore, as is known in the art, data signals are typically latched in relation to a received clocking signal which also may be skewed from the received data signals. One method for correcting this problem is to make the traces (e.g., traces 14a-b) between the I/O pad buffer cells 12 and the receive latches 13 matched. This can be problematic, however, in the design of the electronic circuit on die 1 because other electronic circuits typically appear on the die between the core logic area 11 and the I/O pad buffer cells 12.
In view of the aforementioned problems there is a need for a method and apparatus that provides for the latching of data signals or the like that overcomes these problems.